Method for testing and diagnosing MOS transistors

A method for predicting the operation-time-to-failure of a metal-oxide-semiconductor transistor (MOST) having a gate electrode, and plurality of p/n junctions which can be selectively operated as a lateral bipolar-junction transistor (LBJT) and as a vertical bipolar-junction transistor (VBJT), said MOST having a well p/n junction and an SiO2/Si interface under a metal-electrode-covered gate oxide, the method comprising the steps of:

• (a) forward biasing one of said p/n junctions to serve as an emitter/base junction of a selected one of said LBJT and said VBJT to inject minority carriers into said base body well and said interface under said gate-oxide;
• (b) applying an operating voltage across a another one of said p/n junctions at a level not substantially higher than a predetermined operating voltage which can be safely applied to said MOST during normal operation;
• (c) applying a gate voltage to said gate terminal;
• (d) measuring a DC base current in said MOST, said MOST experiencing a current accelerated stress responsive to said minority carriers in which said DC base current increases with the interface trap concentration in said MOST;
• and,
• (e) predicting said operation-time-to-failure based on said measured DC base current.

A method for monitoring and diagnosing transistor design and fabrication technology for a metal-oxide-semiconductor transistor (MOST) having a gate electrode, two p/n junctions part of whose perimeter is overlapped by the gate electrode, a contact to the base, and with or without a p/n junction well, comprising the steps of:

• (a) operating and diagnosing said MOST without hot carrier stress induced by forward or reverse biasing any of said p/n junctions;
• (b) applying an operating voltage to one of said at least two other terminals at a level not too much higher than a predetermined safe operating voltage which can be applied to said MOST during normal operation;
• (c) applying a varying gate voltage to said gate terminal;
• and,
• (d) measuring a parameter of said base current at a sensitivity on the order of at least femto-amperes.

A method for predicting the operation-time-to-failure of a metal-oxide-semiconductor transistor (MOST) having a gate electrode, a plurality of p/n junctions which can be selectively operated as a lateral bipolar-junction transistor (LBJT) and as a vertical bipolar-junction transistor (VBJT), a well p/n junction, an SiO2/Si interface under a metal-electrode-covered gate oxide, at least two of said plurality of p/n junctions being a source and drain p/n junctions, and a remote p/n junction adjacent to said source and drain p/n junctions, the method comprising the steps of:

• (a) forward biasing said remote p/n junction to inject minority carriers into said base body well and said interface under said gate-oxide;
• (b) applying an operating voltage across one of said plurality of p/n junctions at a level not substantially higher than a predetermined operating voltage which can be safely applied to said MOST during normal operation;
• (c) applying a gate voltage to said gate terminal;
• (d) measuring a DC base current in said MOST, said MOST experiencing a current accelerated stress responsive to said minority carriers in which said DC base current increases with the interface trap concentration in said MOST;
• and,
• (e) predicting said operation-time-to-failure based on said measured DC base current.

A method for monitoring and diagnosing transistor design and fabrication technology for a metal-oxide-semiconductor transistor (MOST) having a gate electrode, two p/n junctions part of whose perimeter is overlapped by the gate electrode, a contact to the base, a very thin gate oxide film enhancing a gate tunneling current, and with or without a p/n junction well, comprising the steps of:

• (a) operating and diagnosing said MOST without hot carrier stress induced by forward or reverse biasing any of said p/n junctions;
• (b) applying an operating voltage to one of said at least two other terminals at a level not too much higher than a predetermined safe operating voltage which can be applied to said MOST during normal operation;
• (c) applying a varying gate voltage to said gate terminal;
• and,
• (d) measuring a parameter of said gate tunneling current.