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AssigneeMicron Technology, Inc.
InventorsAron T. Lunde, Phillip A. Rasmussen
Estimating the term…
A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i.e., the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.
A test board for testing one or more of a plurality of integrated circuits, said test board comprising:
A test system for testing one or more of a plurality of integrated circuits, said test system comprising:
A method for testing one or more integrated circuits on a test board, said test board comprising a plurality of sockets each adapted to receive an integrated circuit being tested, each of said plurality of sockets being connected to a supply voltage through a respective protective device associated with each of said plurality of sockets, said test board further comprising at least one controller to monitor a status of one or more of said respective protective devices, said method comprising the steps of:
Dependencies are inferred from the claim text.