Semiconductor test system having high frequency and low jitter clock generator
AssigneeAdvantest Corporation
InventorShigeki Takizawa
Life of this patent
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Abstract
A semiconductor test system having a high repetition rate and small jitter clock generator for supplying the clock signal to a device under test (DUT). The semiconductor test system includes a clock generator for generating a reference clock signal, a frame processor for producing a clock signal of predetermined waveform based on the reference clock signal from the clock generator, a phase lock loop (PLL) circuit for generating a clock signal based on the clock signal from the frame processor where the frequency generated by the PLL circuit is higher than that of the clock signal from the frame processor, and a driver for directly receiving the clock signal from the PLL circuit to apply the clock signal to the DUT with a predetermined amplitude.
Claims13
A semiconductor test system for testing a semiconductor device (DUT) by applying a clock signal to the DUT, comprising:
- a clock generator for generating a reference clock signal;
- a frame processor for producing a first clock signal of predetermined waveform based on the reference clock signal from the clock generator;
- a phase lock loop (PLL) circuit for generating a second clock signal based on the first clock signal from the frame processor, a frequency of the second clock signal generated by the PLL being higher than that of the first clock signal by predetermined times;
- and a driver for directly receiving the second clock signal from the PLL circuit and applying the second clock signal to the DUT with a predetermined amplitude.
A semiconductor test system for testing a semiconductor device (DUT) by applying a clock signal to the DUT, comprising:
- a clock generator for generating a reference clock signal;
- a first frame processor for producing a first clock signal of predetermined waveform based on the reference clock signal from the clock generator;
- a phase lock loop (PLL) circuit for generating a second clock signal based on the first clock signal from the first frame processor, a frequency of the second clock signal generated by the PLL being higher than that of the first clock signal by predetermined times;
- a second frame processor for producing a gate signal whose time interval represents a specified number of clock pulses of the second clock signal to be applied to the DUT;
- an output control circuit for generating the specified number of pulses of the second clock signal from the PLL circuit based on the gate signal from the second frame processor;
- and
- a driver for applying the specified number of clock pulses from the output control circuit to the DUT with a predetermined amplitude.
A semiconductor test system as defined in claim 8, wherein said PLL circuit further includes a counter for reducing the frequency of the first clock signal from the first frame processor by a predetermined division ratio, and a pre-scaler for dividing the oscillation frequency of the second clock signal from the VCO by a predetermined division ratio.
A semiconductor test system for testing a semiconductor device (DUT) by applying a clock signal to the DUT, comprising:
- a test processor for controlling an overall operation of the semiconductor test system;
- a pattern generator for generating a test pattern signal and an expected value signal based on the instructions from the test processor;
- a timing generator for generating timing signals for defining timings in the semiconductor test system;
- a wave formatter for producing wave forms of the test pattern signal to be applied to the DUT based on the test pattern from the pattern generator and the timing signal from the timing generator;
- a phase lock loop (PLL) circuit for generating a high frequency clock signal based on the wave-formatted test pattern signal from the wave formatter, a frequency of the clock signal generated by the PLL being higher than that of the wave-formatted test pattern signal by predetermined times;
- and
- a driver for directly receiving the clock signal from the PLL circuit and applying the clock signal to the DUT with a predetermined amplitude.
Dependencies are inferred from the claim text.