US 6,275,055 B1Granted

Semiconductor integrated circuit

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsMasahiko Hyozo, Katsushi Asahina

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Abstract

A semiconductor integrated circuit, in which an input buffer, an output buffer, and an input/output buffer connected to signal pins respectively each as an object for a DC test are connected to a single DC test pin through discretely provided switches, all the switches are OFF in an ordinary state, and when the DC test is to be performed, the switches are successively turned ON one by one in a state where the DC test pin is connected to an LSI tester. With the operation, various types of DC test such as a pin contest, an input leak test and an output voltage test can be performed by using a LSI tester having a smaller number of pins than a number of pins in an LSI without requiring a connection such that the signal pins as objects for the test are in one-to-one correspondence with the pin electronics in the LSI tester.

Claims14

Dependent claims

A semiconductor integrated circuit comprising:

a plurality of signal pins each for executing signal transaction to the outside;
at least one signal pin designated for a DC test, when a DC test among a) a test for checking connection between the signal pins and an external connected tester, b) a test for checking a current leak failure to the signal pins provided for signal input from the outside, and c) a test for checking a voltage level output from the signal pins provided for signal output to the outside is executed, said at least one signal pin connected to the external tester;
a plurality of internal circuits connected to the plurality of signal pins respectively and provided for signal transactions to the outside;
and
a plurality of switches, each connected between said at least one signal pin designated for the DC test and a signal path between each of the plurality of internal circuits and the respective remaining signal pin, said plurality of switches for successively connecting the plurality of internal circuits to the at least one signal pin designated for the DC test and said plurality of switches being conductive one by one successively when the DC test is performed.

2 more elements

Dependencies are inferred from the claim text.