Semiconductor device tester and method for testing semiconductor device

A semiconductor device tester for judging a state of a semiconductor device under test by supplying a predetermined test waveform from a driver circuit provided in a pin electronics circuit to said semiconductor device under test through a transmission line, receiving a response waveform from said semiconductor device through said transmission line after a predetermined time from the supply of the predetermined test waveform to said semiconductor device and comparing a state of the response waveform with a predetermined voltage level by an analog comparator, said semiconductor device tester comprising:

• a first transistor connected between said transmission line and an input terminal of said analog comparator, said first transistor being adapted to be turned ON according to a change of the response waveform from High level to Low level for restricting multiple reflection of the response waveform by an output side internal impedance thereof or a combination of the output side internal impedance and an impedance connected in series with the output side internal impedance;
• a second transistor connected between said transmission line and said input terminal of said analog comparator, said second transistor being adapted to be turned ON according to a change of the response waveform from Low level to High level for restricting multiple reflection of the response waveform by an output side internal impedance thereof or a combination of the output side internal impedance and an impedance connected in series with the output side internal impedance;
• a first voltage generator circuit connected to said first transistor for generating a voltage for clamping the level of the response waveform at a certain Low level;
• and
• a second voltage generator circuit connected to said second transistor for generating a voltage for clamping the level of the response waveform at a certain High level.

A multiple reflection restricting circuit of a semiconductor device tester for judging a state of a semiconductor device under test by supplying a predetermined test waveform from a driver circuit provided in a pin electronics circuit to said semiconductor device under test through a transmission line, receiving the response waveform from said semiconductor device through said transmission line after a predetermined time from the supply of the predetermined test waveform to said semiconductor device and comparing a state of the response waveform with a predetermined voltage level by an analog comparator, said multiple reflection restricting circuit comprising:

• a first transistor connected between said transmission line and an input terminal of said analog comparator, said first transistor being adapted to be turned ON according to a change of the response waveform from High level to Low level to restrict a multiple reflection of the response waveform by an output side internal impedance thereof or a combination of the output side internal impedance and an impedance connected in series with the output side internal impedance;
• a second transistor connected between said transmission line and said input terminal of said analog comparator, said second transistor being adapted to be turned ON according to a change of the response waveform from Low level to High level to restrict a multiple reflection of the response waveform by an output side internal impedance thereof or a combination of the output side internal impedance and an impedance connected in series with the output side internal impedance;
• a first voltage generator circuit connected to said first transistor for generating a voltage for clamping the level of the response waveform at a certain Low level;
• and
• a second voltage generator circuit connected to said second transistor for generating a voltage for clamping the level of the response waveform at a certain High level.

A semiconductor device test method for testing a semiconductor device by supplying a predetermined test waveform from a driver circuit provided in a pin electronics circuit to said semiconductor device under test through a transmission line, receiving a response waveform from said semiconductor device under test through said transmission line after a predetermined time from the supply of the predetermined test waveform to said semiconductor device and judging a state of the response waveform by an analog comparator, said semiconductor device test method comprising the steps of:

• turning a first switch circuit connected between said transmission line and an input terminal of said analog comparator ON according to a change of the response waveform from High level to Low level to connect an impedance substantially equal to the characteristic impedance of said transmission line to said transmission line;
• turning a second switch circuit connected between said transmission line and said input terminal of said analog comparator ON according to a change of the response waveform from Low level to High level to connect an impedance substantially equal to the characteristic impedance of said transmission line to said transmission line;
• clamping the response waveform at a certain Low level when the response waveform becomes the certain Low level or lower;
• and
• clamping the response waveform at a certain High level when the response waveform becomes the certain High level or higher.