Circuit for reducing input voltage
AssigneeRobert Bosch GmbH
InventorsAndreas Kneer, Peter Lutz
Life of this patent
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Abstract
A circuit arrangement for reducing a variable, in particular pulsed input voltage (Uein) to an operating voltage Uz, Uarb to be delivered to an evaluation circuit (10), in which the input voltage Uein can be reduced, in accordance with a division factor (F) made available by at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), to obtain the operating voltage Uz, Uarb, in which the at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), can be regulated in such a way that the division factor (F) can be increased with an increasing input voltage Uein and can be decreased with a decreasing input voltage Uein.
Claims10
A circuit arrangement for reducing a variable pulsed input voltage (Uein) to an operating voltage (U or b) to be delivered to an evaluation circuit in which the input voltage (U ein) can be reduced, the circuit arrangement comprising at least one voltage divider (R1, R3, T1, R4;
- R7, R8, R2) including a transistor (T1), the at least one voltage divider providing a division factor according to which the input voltage (U ein) can be reduced so as to obtain the operating voltage (Uarb), the at least one voltage divider being regulated in such a way that the division factor (F) can be increased with an increasing input voltage (U ein) and can be decreased with a decreasing input voltage (U ein), wherein the transistor is a field effect transistor having a control input (G) which can be acted upon by a control voltage derived from one of the operating voltage (Uarb) supplied to the evaluation circuit and an intermediate operating voltage (Us).
A method for reducing a variable, in particular pulsed input voltage (Uein) to an operating voltage (Uarb) to be supplied to an evaluation circuit or an intermediate operating voltage (Us) the method comprising the steps of:
- providing a voltage divider;
- in position of the input voltage (Uein) on the voltage divider (R1, R3, T1, R4) reducing by the voltage divider (R1, R3, T1, R4), the input voltage Uein in accordance with a division factor (F) for attaining the intermediate operating voltage (Us) or the operating voltage (Uarb);
- and
- regulating the voltage divider (R1, R3, T1, R4) in such a way that with an increasing in put voltage Uein, the division factor (F) of the voltage divider (R1, R3, T1, R4) is increased, and with a decreasing input voltage the division factor is decreased.
Dependencies are inferred from the claim text.