Low inductance top metal layer design

A packaged semiconductor device, comprising:

• a substrate having a metal layer providing electrical interconnections, said metal layer including a first conductive area adapted to provide an electrical ground, the first conductive area having a plurality of first conductive finger extensions providing electrical connections to vias for the electrical ground, the first conductive area forming an inside ring having the first conductive finger extensions extending outwardly, said metal layer including a second conductive area adapted to provide an electrical connection to a power supply voltage, the second conductive area having a plurality of second collective finger extensions providing electrical connections to vias for the power supply voltage, the second conductive area forming a concentric outer ring having the second conductive finger extensions extending inwardly, the first conductive finger extensions and the second conductive finger extensions being interlaced to form an intertwined comb structure, the first conductive finger extensions and the second conductive finger extensions being spaced apart a distance substantially equal to a minimum distance allowed by applicable design rules of a manufacturing process used to make the substrate;
• and,
• a semiconductor chip having structures defining circuit device elements, the semiconductor chip being bonded to the substrate,
• a plurality of wires bonded to the semiconductor chip and the substrate to provide electrical interconnection therebetween, wherein a first such wire has one end of such first wire bonded to a pad on the semiconductor chip, and has another end of such first wire bonded to a pad on the substrate which is electrically connected to the first conductive area, and wherein a second such wire has one end of such second wire bonded to a pad on the semiconductor chip, and has another end of such second wire bonded to a pad on the substrate which is electrically connected to the second conductive area.