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US 6,274,921 B1Granted
Semiconductor integrated circuit including protective transistor protecting another transistor during processing
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKouichi Hasegawa
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Abstract
A semiconductor integrated circuit has a protective NMOS transistor having a drain and a source respectively electrically connected to a first interconnection (electrically connected to a base electrode of a bipolar transistor or a gate electrode of a MOS transistor) and ground and a gate electrode in a floating state, upon formation of the first interconnection. The first interconnection is formed by patterning using plasma etching and is connected to ground after the formation of the first interconnection.
Claims10
A semiconductor integrated circuit comprising:
- a bipolar transistor;
- an interconnection electrically connected to a base electrode of said bipolar transistor;
- and
- a protective NMOS transistor having a drain electrically connected to said interconnection, a source electrically connected to ground and a gate electrode placed in a floating state during formation of said interconnection by patterning through plasma etching, said protective NMOS transistor being in an OFF state free of of a current flow between the source and the drain after formation of said interconnection.
1 more element
A semiconductor integrated circuit comprising:
- an MOS transistor;
- an interconnection electrically connected to a gate electrode of said MOS transistor;
- and
- a protective NMOS transistor having a drain electrically connected to said interconnection, a source electrically connected to a ground and a gate electrode placed in a floating state during formation of said interconnection by patterning through plasma etching, said protective NMOS transistor being in an OFF state free of current flow between the source and the drain after the formation of said interconnection.
1 more element
Dependencies are inferred from the claim text.