Shielded channel transistor structure with embedded source/drain junctions

Abstract

Microelectronic structures embodying the present invention include a silicon pillar contiguous with a bulk semiconductor, the pillar being surrounded by a shallow trench isolation insulator, which has been recessed to receive polysilicon and a superjacent layer of silicon deposited thereon. Source and drain (S/D) terminals are formed in the silicon of the recessed portions of the shallow trench isolation insulator. In this way the S/D terminals are substantially isolated from the body, thereby substantially reducing both parasitic junction capacitance and junction leakage currents. Isolation of S/D terminals in this way also reduces the degradation of effective channel length that can otherwise occur in MOSFETs.

Dependencies are inferred from the claim text.