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AssigneeSony Corporation
InventorsKazumasa Nomoto, Dharam Pal Gosain, Setsuo Usui, Takashi Noguchi
Estimating the term…
A memory device, a manufacturing method thereof, and an integrated circuit thereof are provided for storing information over a long period of time even if the memory device is manufactured at low temperatures. On a substrate made of glass, etc., a memory transistor and a selection transistor are formed, with a silicon nitride film and a silicon dioxide film in between. The memory transistor and the selection transistor are connected in series at a second impurity region. The conduction region for memory of the memory transistor is made of non-single crystal silicon and a storage region comprises a plurality of dispersed particulates made of non-single crystal silicon. Therefore, electrical charges can be stored partially if a tunnel insulating film has any defects. The tunnel insulating film is formed by exposing the surface of the conduction region for memory to the ionized gas containing oxygen atoms.
A memory device comprising:
An integrated circuit integrated with a plurality of memory devices, wherein each of the memory devices comprises a base portion made of an insulator, a conduction region for memory made of a semiconductor provided on one surface of the base portion, a first impurity region provided adjacent to the conduction region for memory, a second impurity region separated from the first impurity region and provided adjacent to the conduction region for memory, a storage region comprising a plurality of dispersed particulates for accumulating electrical charges moved from the conduction region for memory, a tunnel insulating film provided between the storage region and the conduction region for memory, a control electrode for memory for controlling the electrical charge amount of the storage region and the conductivity of the conduction region for memory, an insulating film for controlling memory provided between the control electrode for memory and the storage region, a conduction region for selection provided on one surface of the base portion, which is adjacent to the second impurity region and separated from the conduction region for memory, a third impurity region provided adjacent to the conduction region for selection and separated from the second impurity region, a control electrode for selection for controlling the conductivity of the conduction region for selection;
Dependencies are inferred from the claim text.