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US 6,274,887 B1Granted
Semiconductor device and manufacturing method therefor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
Life of this patent
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Abstract
An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
Claims81
A semiconductor device comprising a thin film transistor including:
- an active layer;
- a wiring being formed over the active layer having an insulating film interposed therebetween;
- and
- at least a sidewall being formed on a side portion of the wiring,
- wherein the active layer has a channel forming region, at least a first impurity region, at least a second impurity region, and at least a third impurity region,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein the first impurity region is in contact with the channel region and overlap the sidewall through the insulating film.
4 more elements
A semiconductor device comprising a thin film transistor including:
- an active layer;
- a wiring being over the active layer having an insulating film interposed therebetween;
- and
- at least a sidewall being formed on a side portion of the wiring,
- wherein the active layer has a channel forming region, at least a first impurity region, at least a second region and at least a third region, each of which being aligned in order,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein the first impurity region is in contact with the channel region and overlap the sidewall through the insulating film.
4 more elements
A semiconductor device comprising a thin film transistor having:
- an active layer;
- a wiring being formed over the active layer having an insulating film interposed therebetween, and
- at least a sidewall being formed on a side portion of the wiring,
- wherein the active layer has a channel forming region, at least a first impurity region, at least a second impurity region, and at least a third impurity region,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein concentrations of the impurity in the first, second and third impurity regions increase as distances from the channel forming region become longer.
3 more elements
A semiconductor device comprising a thin film transistor having:
- an active layer,
- a wiring being formed over the active layer having an insulating film, and
- at least a sidewall being formed on a side portion of said wiring,
- wherein the active layer has a channel forming region, at least a first impurity region, at least a second region and at least a third region, each of which being aligned in order,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein the second impurity region includes the impurity at a higher concentration than the first impurity region while the third impurity region includes the impurity at a higher concentration than the second impurity region.
3 more elements
A semiconductor device comprising a CMOS circuit including:
- an NTFT having:
- a first active layer,
- a first wiring being formed over the first active layer having a first insulating film interposed therebetween, and
- at least a sidewall being formed on a side portion of the first wiring, and
- a PTFT having:
- a second active layer, and
- a second wiring being formed over the second active layer having a second insulating film interposed therebetween,
- wherein the first active layer of the NTFT has a first channel forming region, at least a first impurity region, at least a second impurity region, and at least a third impurity region,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein the first impurity region is in contact with the first channel region and overlap the sidewall through the first insulating film.
7 more elements
A semiconductor device comprising a CMOS circuit including:
- an NTFT having:
- a first active layer,
- a first wiring being formed over the first active layer having a first insulating film interposed therebetween, and
- at least a sidewall being formed on a side portion of the first wiring, and
- a PTFT having:
- a second active layer, and
- a second wiring being formed over the second active layer having a second insulating film interposed therebetween,
- wherein the first active layer of the NTFT has a first channel forming region, at least a first impurity region, at least a second impurity region, and at least a third impurity region, each of which being aligned in order,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein the first impurity region is in contact with the first channel region and overlap the sidewall through the first insulating film.
7 more elements
A semiconductor device comprising a CMOS circuit including:
- an NTFT having:
- a first active layer,
- a first wiring being formed over the first active layer having a first insulating film interposed therebetween, and
- at least a sidewall formed on a side portion of the first wiring, and
- a PTFT having:
- a second active layer, and
- a second wiring being formed over the second active layer having a second insulating film interposed therebetween,
- wherein the first active layer of the NTFT has a first channel forming region, at least a first impurity region, at least a second impurity region, and at least a third impurity region,
- wherein each of the first, second and third impurity regions has a same impurity,
- wherein concentrations of the impurity in the first, second and third impurity regions increase as distances from the channel forming region become longer.
7 more elements
A semiconductor device comprising a CMOS circuit including:
- an NTFT having:
- a first active layer,
- a first wiring being formed over the first active layer having a first insulating film interposed therebetween, and
- at least a sidewall being formed on a side portion of the first wiring, and
- a PTFT having:
- a second active layer, and
- a second wiring being formed over the second active layer having a second insulating film interposed therebetween,
- wherein the first active layer of the NTFT has a first channel forming region, at least a first impurity region, at least a second impurity region, and at least a third impurity region, each of which being aligned in order,
- wherein each of the first, second and third impurity regions has a same impurity at a different concentration,
- wherein the second impurity region includes the impurity at a higher concentration than the first impurity region while the third impurity region includes the impurity at a higher concentration than the second impurity region.
7 more elements
An electroluminescence display device comprising:
- a pixel portion and a peripheral driving circuit portion over a substrate;
- at least a first thin film transistor for controlling a current and a second thin film transistor for switching each being formed in the pixel portion;
- at least a CMOS transistor being formed in the peripheral driving circuit portion;
- wherein the first thin film transistor includes:
- a semiconductor island over the substrate;
- a channel forming region in the semiconductor island;
- at least a first impurity region being in contact with the channel forming region;
- at least a second impurity region being in contact with the first impurity region;
- at least a third impurity region being in contact with the second impurity region;
- a gate insulating film being formed on the channel forming region, the first impunity region and the second impurity region;
- a gate electrode being formed over the channel forming region with the gate insulating film interposed therebetween;
- at least a sidewall being formed over the first impurity region and being conductive;
- a pixel electrode being electrically connected to the third impurity region of the first thin film transistor;
- a light emitting layer being formed over the pixel electrode;
- an electrode being formed over the light emitting layer.
12 more elements
Dependencies are inferred from the claim text.