US 6,274,509 B1 · Global planarization method for inter-layer-dielectric and inter-metal dielectric

Abstract

A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material. The planarizing method of the invention has the advantage of not requiring a photolithography step required in a prior art planarization process. In addition, the planarization method of the invention has the advantage of not requiring a process step that subjects an integrated circuit to relatively high temperatures that can have adverse effects on metal conductors present therein.

Claims19

Dependent claims

A method of planarizing a dielectric layer having an irregular top surface topology including a first higher and a first lower regions, wherein said first higher region includes first upper and first lower portions, the method comprising the steps of:

forming a substantially conformal layer of sacrificial oxide over said first higher and first lower regions of said dielectric layer, wherein said sacrificial oxide layer includes corresponding second higher and second lower regions, and said second higher region includes second upper and second lower portions coincident with said first upper and first lower portions of said dielectric layer;
forming a substantially conformal layer of amorphous silicon over said second higher and second lower regions of said sacrificial oxide layer, wherein said amorphous silicon layer includes corresponding third upper and third lower regions, and said third upper region includes third upper and third lower portions coincident with said second upper and second lower portions of said sacrificial oxide layer;
removing said third upper portion of said amorphous silicon layer to substantially expose said second upper portion of said sacrificial oxide layer;
removing said second upper portion of said sacrificial oxide layer to form a channel within said sacrificial oxide layer;
and
polishing off the remaining sacrificial oxide and amorphous silicon, and a portion of said dielectric layer to substantially planarize the top surface thereof.

3 more elements

Dependencies are inferred from the claim text.

Global planarization method for inter-layer-dielectric and inter-metal dielectric

Life of this patent

Global planarization method for inter-layer-dielectric and inter-metal dielectric

Life of this patent

Abstract

Claims19