Formation of structure to accurately measure source/drain resistance
AssigneeAdvanced Micro Devices, Inc.
InventorsConcetta Riccobene, Ognjen Milic-Strkalj
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsConcetta Riccobene, Ognjen Milic-Strkalj
Estimating the term…
A method is provided for directly measuring the source/drain resistance of a metal oxide semiconductor (MOS) device. Embodiments include partially deconstructing a typical MOS device by removing its gate and gate oxide from the substrate, as by etching, while preserving its gate sidewall spacer (typically silicon nitride). A sacrificial oxide spacer is formed on the nitride spacer, as by anisotropically etching a deposited oxide layer, and the area surrounding the sacrificial oxide spacer is filled with a layer of nitride. The sacrificial oxide spacer is then selectively etched to expose a portion of the main surface of the substrate and leave the nitride spacer and layer, thus creating a location near the edge of a source/drain region for a metal contact to be formed, as by chemical vapor deposition (CVD). The source/drain resistance of the device can then be directly and accurately measured by making electrical contact to the newly formed contact and a pre-existing source/drain contact on the same active area.
A method for forming an electrical contact on a main surface of a semiconductor substrate to an active region in the substrate, wherein a gate oxide layer is disposed on a portion of the active region and extends over an edge of the active region, a gate is disposed on the gate oxide layer, and a sidewall spacer of a dielectric material is disposed on a sidewall of the gate and extends onto the active region, the method comprising:
Dependencies are inferred from the claim text.