Method to avoid copper contamination during copper etching and CMP

A method of preventing copper contamination of a dielectric layer during chemical mechanical polishing in the fabrication of an integrated circuit device comprising:

• providing said dielectric layer overlying a semiconductor substrate;
• depositing a dielectric cap layer overlying said dielectric layer;
• forming a dual damascene opening through said dielectric cap layer and said dielectric layer;
• depositing a barrier metal layer overlying said dielectric cap layer and within said dual damascene opening;
• depositing a copper layer overlying said barrier metal layer and filling said dual damascene opening;
• and
• polishing back said copper layer to leave said copper layer only within said dual damascene opening wherein said dielectric cap layer prevents said copper contamination of said dielectric layer during said polishing.

A method of preventing copper contamination of a dielectric layer in the fabrication of an integrated circuit device comprising:

• providing said dielectric layer overlying a semiconductor substrate;
• depositing a first dielectric cap layer overlying said dielectric layer;
• forming a dual damascene opening through said first dielectric cap layer and said dielectric layer;
• depositing a barrier metal layer overlying said first dielectric cap layer and within said dual damascene opening;
• depositing a copper layer overlying said barrier metal layer and filling said dual damascene opening;
• polishing back said copper layer and said barrier metal layer to leave said copper layer and said barrier metal layer only within said dual damascene opening wherein said first dielectric cap layer prevents said copper contamination of said dielectric layer during said polishing;
• etching said copper layer to form a recess within said dual damascene opening;
• depositing a second dielectric cap layer overlying said barrier metal layer and said copper within said recess;
• coating a spin-on material overlying said second dielectric cap layer;
• etching back said spin-on material and said first and second dielectric cap layer over said dielectric layer whereby all of said first dielectric cap layer is removed;
• and
• thereafter removing all of said spin-on material leaving said second dielectric cap layer only over said copper within said recess wherein said second dielectric cap layer prevents said copper contamination in the fabrication of said integrated circuit device.

A method of preventing copper contamination of a dielectric layer in the fabrication of an integrated circuit device comprising:

• providing said dielectric layer overlying a semiconductor substrate;
• depositing a first dielectric cap layer overlying said dielectric layer;
• forming a dual damascene opening through said first dielectric cap layer and said dielectric layer;
• depositing a barrier metal layer overlying said first dielectric cap layer and within said dual damascene opening;
• depositing a copper layer overlying said barrier metal layer and filling said dual damascene opening;
• polishing back said copper layer and said barrier metal layer to leave said copper layer and said barrier metal layer only within said dual damascene opening wherein said first dielectric cap layer prevents said copper contamination of said dielectric layer during said polishing;
• etching said copper layer to form a recess within said dual damascene opening;
• depositing a second dielectric cap layer overlying said barrier metal layer and said copper within said recess;
• forming a mask over said dual damascene opening and etching away said first and second dielectric cap layers where they are not covered by said mask;
• and
• thereafter removing said mask leaving said second dielectric cap layer only over said copper within said recess wherein said second dielectric cap layer prevents said copper contamination in the fabrication of said integrated circuit device.