Copper damascene manufacturing process

A copper damascene process, comprising the steps of:

• providing a substrate;
• forming a metal layer over the substrate;
• forming an amorphous silicon layer over the metal layer;
• patterning the amorphous silicon layer and the metal layer to form a conductive structure above the substrate;
• forming a silicon nitride liner layer over the conductive structure and the substrate;
• forming a low dielectric constant layer over the silicon nitride liner layer;
• forming a dielectric cap layer over the low dielectric constant layer;
• forming a silicon nitride layer over the dielectric cap layer;
• patterning the silicon nitride layer, the dielectric cap layer, the low dielectric constant layer and the silicon nitride liner layer to form a via that exposes a portion of the amorphous silicon layer of the conductive structure;
• forming a metal barrier layer over the silicon nitride layer, sidewalls of the via and the amorphous silicon layer;
• etching to remove the metal barrier layer above the silicon nitride layer and the amorphous silicon layer to form metal barrier spacers on the sidewalls of the via;
• performing a copper displacement operation so that the amorphous silicon layer is replaced by a first copper layer and a portion of the metal barrier spacers is replaced by a second copper layer;
• removing the second copper layer above the metal barrier spacers;
• and
• performing a copper electroless plating using the first copper layer as a seeding layer to form a copper plug inside the via.