Process using a plug as a mask for a gate
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
Estimating the term…
Abstract
A method of fabricating an integrated circuit with a gate structure comprised of an oxide/polysilicon/metal stack. The method includes forming the gate structure by using a metal plug as a hard mask in place of a hard mask produced using photolithography. Thus, linewidth limitations of conventional photolithography do not apply. Specifically, the method includes providing a pattern over a semiconductor substrate; partially filling the pattern with a polysilicon material such that a trench is left in the polysilicon material, and filling the trench in the polysilicon material with metal to form a plug. After forming the materials, excess materials are removed leaving the gate structure.
Claims20
A method of manufacturing an integrated circuit, comprising:
- providing a semiconductor substrate;
- providing a patterned layer over the substrate including at least one pattern aperture, whereby the pattern aperture defines at least part of an active area of the substrate;
- forming a first material over the patterned layer, wherein the pattern aperture is partially filled with the first material and a trench is formed in the first material that corresponds to the location of the pattern aperture;
- forming a second material over the first material, wherein the second material is a metal material, wherein a plug is formed where the second material substantially fills the trench;
- and
- removing a portion of the second material, wherein the plug remains in the trench, whereby the plug provides a hard mask for a gate conductor, the gate conductor including the first material and the plug.
A method of forming a gate structure for a transistor on an integrated circuit, the method comprising:
- providing a semiconductor substrate;
- providing a first material disposed over the substrate, wherein the first material includes a trench;
- substantially filling the trench with a second material to form a plug, whereby the plug provides a non-insulative hard mask;
- and
- removing a portion of the first material, wherein the first material remains below the plug, whereby a gate structure including the plug and the first material is formed over the substrate.
A method of forming a gate structure for a transistor on an integrated circuit on a semiconductor substrate, the gate structure having a gate width less than a lithographic feature, the method comprising:
- providing an aperture in a first material disposed above the substrate, the aperture having a width of approximately the lithographic feature;
- conformally depositing the second material in the aperture, the second material having a second aperture;
- conformally depositing a third material within the second aperture;
- removing the third material to leave a plug in the second aperture;
- and
- removing the second material using the plug as a non-insulative hard mask, wherein the second material remains below the plug, whereby a gate structure including the plug and the second material is formed over the substrate.
Dependencies are inferred from the claim text.