Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap
AssigneeInternational Business Machines Corporation
InventorsPaul D. Agnello, Peter I. Smeys
Life of this patent
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Abstract
A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.
Claims18
A method of forming a semiconductor device structure, the method comprising:
- forming a gate oxide region on a semiconductor substrate;
- forming a gate structure on the gate oxide region;
- forming an oxide layer on the semiconductor substrate and gate structure;
- implanting source and drain extension regions in the semiconductor substrate;
- forming first, sidewall spacer regions on sides of the gate structure;
- forming second spacer regions on sides of the sidewall spacer regions;
- implanting deep source and drain regions in the semiconductor substrate;
- removing the oxide layer on the gate structure and on the sides of the gate structure in the vicinity of the top of the gate structure;
- and
- siliciding the gate structure and the sidewall spacer regions in the vicinity of the top of the gate structure and the sidewall spacer regions and siliciding portions of the source and drain extension regions not covered by the sidewall spacer regions or the second spacer regions.
Dependencies are inferred from the claim text.