US 6,274,443 B1Granted

Simplified graded LDD transistor using controlled polysilicon gate profile

AssigneeAdvanced Micro Devices, Inc.

InventorsAllen S. Yu, Patrick K. Cheung, Paul J. Steffan

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Abstract

An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.

Claims13

Dependent claims

A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;
forming a polysilicon layer over said gate oxide layer;
forming a first mask layer over said polysilicon layer;
patterning and etching said first mask layer to form a first gate mask;
anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;
implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions and a doped resistor region in the semiconductor substrate;
anisotropically etching said first polysilicon gate to form a second polysilicon gate using said first gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;
removing said first gate mask;
forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;
selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;
anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate;
and
removing said resistor protect mask to expose said resistor isolation.

10 more elements

A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;
forming a polysilicon layer over said gate oxide layer;
forming a first mask layer over said polysilicon layer, wherein said first mask layer is a material selected from the group consisting of oxide and nitride;
forming a second mask layer over said first mask layer and patterning and etching said second mask layer to form a first gate mask;
patterning and etching said first mask layer to form a second gate mask;
anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;
implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions and a doped resistor region in the semiconductor substrate, wherein said dopant penetrates portions of said sidewalls to form said shallow extension junctions, said shallow extension junctions are graded junctions;
anisotropically etching said first polysilicon gate to form a second polysilicon gate using said second gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;
removing said second gate mask;
forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;
selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;
anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate;
and
removing said resistor protect mask to expose said resistor isolation.

11 more elements

A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;
forming a polysilicon layer over said gate oxide layer;
forming a first mask layer over said polysilicon layer, wherein said first mask layer is a material selected from the group consisting of oxide and nitride;
forming a second mask layer over said first mask layer and patterning and etching said second mask layer to form a first gate mask;
patterning and etching said first mask layer to form a second gate mask;
anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;
implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions, deep junctions in a portion of the semiconductor substrate not shielded by said first polysilicon gate and adjacent said shallow extension junctions, and a doped resistor region in the semiconductor substrate, wherein said dopant penetrates portions of said sidewalls to form said shallow extension junctions, said shallow extension junctions are graded junctions;
anisotropically etching said first polysilicon gate to form a second polysilicon gate using said second gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;
removing said second gate mask;
forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;
selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;
anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate, wherein the step of anisotropically etching said resistor protect layer includes the step of over-etching said resistor protect layer to reduce the dimensions of said first sidewall spacer so that the top portion of said second polysilicon gate is exposed;
and
removing said resistor protect mask to expose said resistor isolation.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/162,116Filed 28 Sep 1998
Granted: 14 Aug 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/0229
Having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped…
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions