Fabrication method for a high voltage electrical erasable programmable read only memory device

A fabrication method for a high voltage electrically erasable read only memory device, which is applicable on a substrate and the substrate comprises a memory device region and a peripheral high voltage circuit region, wherein a floating gate and a select-gate are formed on the substrate in the memory device region and a gate electrode is formed on the substrate in the peripheral high voltage circuit region, the method comprising:

• forming an oxide/nitride/oxide layer on the substrate;
• forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer exposes the oxide/nitride/oxide layer in the peripheral high voltage circuit region and a portion of the oxide/nitride/oxide layer in the memory device region;
• removing a portion of an upper oxide layer of the oxide/nitride/oxide layer using the photoresist layer as a mask;
• removing the patterned photoresist layer;
• removing a portion of the nitride layer of the oxide/nitride/oxide layer;
• performing a double diffused ion implantation to form a double diffused drain structure in the substrate on both sides of the gate electrode;
• oxidizing an lower oxide layer of the oxide/nitride/oxide layer to form a bird's beak structure at a bottom corner of the gate electrode;
• forming a control gate on the oxide/nitride/oxide layer in the device region, wherein the control gate, the oxide/nitride/oxide layer, and the floating gate form an electrically erasable read only memory having a split gate;
• and
• forming a first source/drain region that comprises the double diffused drain structure in the substrate on both sides of the gate electrode, and a second source/drain region in the substrate on one side of the floating gate.

A fabrication method for a high voltage electrically erasable read only memory, which is applicable on a substrate and the substrate comprises a memory device region and a peripheral high voltage circuit region, wherein a floating gate is formed on the substrate in the memory device region and a gate electrode is formed on the substrate in the peripheral high voltage circuit region, comprising

• forming an oxide/nitride/oxide layer on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer;
• removing the second oxide layer in the peripheral high voltage circuit region;
• removing the nitride layer in the peripheral high voltage circuit region;
• oxidizing the first oxide layer and performing a double diffused drain implantation to form a bird's beak structure at a bottom corner of the gate electrode and to form a double diffused drain structure in the substrate on both sides of the gate electrode;
• forming a control gate on the oxide/nitride/oxide layer in the memory device region;
• and
• forming a first source/drain region that comprises the double diffused drain structure in the substrate on both sides of the gate electrode, and a second source/drain region in the substrate on one side of the floating gate.