Method of manufacturing flash memory cell
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsSang Soo Kim, Sung Mun Jung, Kwi Wook Kim
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Abstract
The present invention relates to a method of manufacturing a flash memory cell. In order to solve a problem that a reliability of a device is degraded according as electron injected into a floating gate leaks to an exterior due to various stimulus, the floating gate of the flash memory cell is formed dividely into a upper layer and a lower layer with respect to a charge barrier layer so that the leakage of the electrons injected into the floating gate can be prevented from external stimulus, thereby improving a reliability of the memory device.
Claims6
A method of manufacturing a flash memory cell, comprising the steps of:
- a) forming a first polysilicon layer on a semiconductor substrate having a gate oxide layer;
- b) forming a charge barrier layer on said first polysilicon layer;
- c) forming a second polysilicon layer on said charge barrier layer;
- d) patterning said second polysilicon layer, said charge barrier layer and said first polysilicon layer thereby to form a floating gate having said second polysilicon layer and said first polysilicon layer divided by said charge barrier layer;
- and
- e) forming a dielectric layer and a third polysilicon layer for a control gate on an entrie structure and patterning said dielectric layer and said third polysilicon layer by using a self-alignment etching process, thereby to form a control gate.
A method of manufacturing a flash memory cell, comprising the steps of:
- a) forming a first polysilicon layer on a semiconductor substrate having a gate oxide layer;
- b) forming a charge barrier layer on said first polysilicon layer;
- c) forming a second polysilicon layer on said charge barrier layer;
- d) forming a floating gate by patterning said second polysilicon layer, said charge barrier layer and said first polysilicon layer;
- e) forming a dielectric layer on the floating gate;
- f) forming a third polysilicon layer on the dielectric layer;
- and
- g) forming a control gate by patterning the third polysilicon layer and the dielectric layer with a self-alignment etching process such that at least a portion of the third polysilicon layer remains on the dielectric layer.
Dependencies are inferred from the claim text.