Self-aligned Vt implant

A method of manufacturing a transistor, comprising:

• forming a doped region in an active area of a substrate, the doped region having a first conductivity type and a first horizontal junction;
• forming a first source/drain region of the first conductivity type in the active area with a second horizontal junction;
• forming a second source/drain region of the first conductivity type in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region, the second and third horizontal junctions being positioned substantially at the first horizontal junction;
• doping the portion of the doped region positioned in the channel region with an impurity of a second conductivity type that is opposite to the first conductivity type;
• and
• forming a gate insulating layer on the substrate and a gate electrode on the gate insulating layer.

A method of manufacturing, comprising:

• forming a doped region in an active area of a substrate, the doped region having a first conductivity type and a first horizontal junction;
• forming a temporary gate on a substrate;
• forming a first source/drain region of the first conductivity type in the active area with a second horizontal junction;
• forming a second source/drain region of the first conductivity type in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region, the second and third horizontal junctions being positioned substantially at the first horizontal junction;
• forming an insulating layer on the substrate adjacent to the temporary gate;
• removing the temporary gate to leave an opening in the insulating layer;
• and
• doping the channel region by implanting an impurity species through the opening and into the channel region, the impurity species having a second conductivity type that is opposite to the first conductivity type.