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US 6,274,412 B1Granted
Material and method for printing high conductivity electrical conductors and other components on thin film transistor arrays
AssigneeParelec, Inc.
InventorsPaul H. Kydd, Sigurd Wagner, Helena Gleskova
Life of this patent
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Abstract
A process sequence is disclosed for fabricating arrays of Thin Film Transistors by printing metallic conductors for the gate and data lines and possibly the Indium Tin Oxide Pixel electrode as well. The process eliminates conventional step-and-repeat photolithographic patterning, and provides high conductivity metallization for large arrays. These arrays may be used in displays, detectors and scanners.
Claims7
A method for producing an array of one or more Thin Film Transistors comprising the steps of:
- a) printing a pattern of one or more high conductivity metallic gate lines on a substrate;
- b) covering said gate lines with a layer having a first sub-layer comprised of a silicon nitride gate dielectric, a second sub-layer comprised of a-Si:H, and a third sub-layer comprised of (n+) a-Si:H;
- c) printing a pattern of one or more sets of drain, source, and data line conductors;
- d) depositing one or more Indium Tin Oxide pixels;
- wherein said gate lines are printed by applying a composition comprising a Reactive Organic Medium (ROM) and metal in a pattern of said one or more gate lines and then heating said pattern to form metal conductors.
2 more elements
Dependencies are inferred from the claim text.