Tri-layer process for forming TFT matrix of LCD with reduced masking steps
AssigneeHannstar Display Corp.
InventorTean-Sen Jen
Life of this patent
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Abstract
A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique twice, two masking steps for patterning an etch stopper layer, and an upper doped and a lower intrinsic semiconductor layers, respectively, can be omitted. Further, owing to the back-exposing energy for patterning the semiconductor layers is less than that for patterning the etch stopper layer, the resulting etch stopper layer is enclosed with the resulting semiconductor layers, and the contact of the two semiconductor layers can be achieved.
Claims25
A process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), comprising steps of:
- providing a substrate made of an insulating material;
- forming a first conductive layer on a first side of said substrate, and using a first masking and patterning procedure to remove a portion of said first conductive layer to define a scan line and a gate electrode of a TFT unit;
- successively forming an insulation layer, a semiconductor layer, an etch stopper layer, and a first photoresist layer on said substrate with said scan line and said gate electrode;
- providing a first exposing source from a second side of said substrate opposite to said first side by using said scan line and said gate electrode as shields to obtain a first exposed area and a first unexposed area;
- removing said first photoresist layer, and said etch stopper layer of said first exposed area so that the remaining portion of said etch stopper layer in said first unexposed area has a specific shape similar to the shape of said scan line together with said gate electrode;
- forming a doped semiconductor layer and a second photoresist layer on said substrate with said etch stopper layer of said specific shape;
- providing a second exposing source from a second side of said substrate opposite to said first side by using said scan line and said gate electrode as shields to obtain a second exposed area and a second unexposed area;
- removing said second photoresist layer, said doped semiconductor layer of said second exposed area, and said semiconductor layer of said second exposed area so that shapes of remaining portions of said doped semiconductor layer and said semiconductor layer in said second unexposed area are similar to that of said etch stopper layer of said specific shape, but have areas larger than that of said etch stopper layer of said specific shape, thereby making said doped semiconductor layer in contact with said semiconductor layer;
- successively forming a transparent conductive layer and a second conductive layer on said substrate, and using a second masking and patterning procedure to remove a portion of said transparent conductive layer and a portion of said second conductive layer to define a pixel electrode region and data and connection lines, respectively;
- removing another portion of said doped semiconductor layer with a remaining portion of said second conductive layer as shields to define source/drain regions;
- forming a passivation layer on said substrate, and using a third masking and patterning procedure to remove a portion of said passivation layer;
- and
- removing another portion of said second conductive layer in said pixel electrode region with said patterned passivation layer as shields to define a pixel electrode.
Dependencies are inferred from the claim text.