US 6,272,668 B1Granted

Method for cell swapping to improve pre-layout to post-layout timing

AssigneesHyundai Electronics America, NCR Corporation

InventorAndres R. Teene

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Abstract

A method for improving the timing performance of a standard cell ASIC layout. The method is operable at any phase of the ASIC design cycle including following the completion of layout phase placement and routing. The method compares post-layout timing values with pre-layout timing targets for each timing arc associated with each standard cell component of the ASIC design. For each timing arc, a functionally equivalent cell having higher or lower output drive is selected which optimally improves the timing slack on each timing arc. To assure that the method converges and terminates, a list of timing slack values, one for each timing arc of the ASIC design, is constructed in sorted order from worst timing slack to best timing slack. The swap method determines in order from worse timing slack to best a functionally equivalent standard cell which may be swapped to improve the timing slack on the timing arc. Once a standard cell is swapped for a given timing arc, no further swaps need be made for subsequent entries on the sorted list: the timing slack of subsequent entries is assured to be better than the worse timing slack value of an earlier encountered timing arc in the sorted list.

Claims23

Dependent claims

A method for improving the timing performance of an ASIC layout, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:

placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a timing slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing, determining a post-layout timing and calculating a timing slack value steps for each timing arc of each standard cell circuit component in order to generate a list of at least one timing slack value which corresponds to each timing arc;
determining a timing difference between the standard cell circuit component associated with a timing arc in said list and at least one logically equivalent second standard cell circuit component;
calculating a slack change value by subtracting said timing difference from the timing slack value associated with the said timing arc in said list;
repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component logically equivalent to said standard cell circuit component;
identifying which said slack change value, calculated by operation of said step of repeating said determining a timing difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said timing arc on said list in order to generate an optimum timing slack value;
swapping said standard cell circuit component associated with said timing arc on said list with the second standard cell circuit component associated with said optimum timing slack value to improve timing performance of said ASIC layout;
and
repeating said steps of determining a timing difference, calculating a slack change value, repeating said determining a timing difference and calculating a slack change value steps for each second standard cell circuit component, identifying, and swapping for each timing arc on said list.

10 more elements

A method for improving the performance of an ASIC layout with respect to a predetermined parameter, said ASIC having at least one standard cell circuit component and at least one timing arc associated with said standard cell circuit component, said method comprising the steps of:

placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routing steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a performance slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing target value, determining a post-layout timing value and calculating a performance slack value steps for each timing arc for each standard cell circuit component in order to generate a list of at least one performance slack value which corresponds to each timing arc;
determining a performance difference between the standard cell circuit component associated with a timing arc in said list and at least one logically equivalent second standard cell circuit component;
calculating a slack change value by subtracting said performance difference from the performance slack value associated with the said timing arc in said list;
repeating said determining a performance difference and calculating a slack change value steps for each second standard cell circuit component logically equivalent to said standard cell circuit component;
identifying which said slack change value calculated by operation of said step of repeating said determining a performance difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said predetermined parameter of said timing arc on said list in order to generate an optimum performance slack value;
swapping said standard cell circuit component associated with said timing arc on said list with the second standard cell circuit component associated with said optimum performance slack value to improve performance of said ASIC layout with respect to said predetermined parameter;
and
repeating said steps of determining a performance difference, calculating a slack change value, repeating said determining a performance difference and calculating a slack change value steps for each second standard cell circuit component, identifying, and swapping for each timing arc on said list.

10 more elements

A method for improving the performance of an ASIC layout with respect to a predetermined parameter, said ASIC having at least one circuit component and at least one timing arc associated with said at least one circuit component said method comprising the steps of:

placing all circuits in the ASIC layout;
routing all timing arcs in the ASIC layout;
generating a pre-layout timing target value for a timing arc of said ASIC automatically based on historical statistical information regarding the ASIC layout before said placing and routine steps;
determining a post-layout timing value for said timing arc after said placing and routing steps;
calculating a performance slack value for said timing arc by subtracting said post-layout timing value from said pre-layout timing target value;
repeating said generating a pre-layout timing target value, determining a post-layout timing value and calculating a performance slack value steps for each timing arc for each circuit component in order to generate a list of at least one performance slack value which corresponds to each timing arc;
determining a performance difference between the circuit component associated with a timing arc in said list and at least one logically equivalent second circuit component;
calculating a slack change value by subtracting said performance difference from the performance slack value associated with the said timing arc in said list;
repeating said determining a performance difference and calculating a slack change value steps for each second circuit component logically equivalent to said circuit component;
identifying which said slack change value,calculated by operation of said step of repeating said determining a performance difference and calculating a slack change value steps, most improves performance of said ASIC with respect to said predetermined parameter of said timing arc on said list in order to generate an optimum performance slack value;
swapping said circuit component associated with said timing arc on said list with the second circuit component associated with said optimum performance slack value to improve performance of said ASIC layout with respect to said predetermined parameter;
and
repeating said steps of determining a performance difference, calculating a slack change value, repeating said determining a performance difference and calculating a slack change value steps for each second circuit component, identifying, and swapping for each timing arc on said list.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/318,388Filed 25 May 1999 · continuation
Priority: 14 Dec 1994
Granted: 7 Aug 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/39
Circuit design: circuit design at the physical level
G06F 2119/06
Details relating to the type or aim of the analysis or the optimisation: power analysis or power optimisation
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation