Transistor group mismatch detection and reduction

Abstract

In some embodiments, the invention includes a system having first and second domains. The system includes a first performance detection circuitry including some transistors of the first domain to provide a first performance rating signal indicative of transistor switching rates of the first domain. The system includes second performance detection circuitry including some transistors of the second domain to provide a second performance rating signal indicative of transistor switching rates the second domain. The system further includes control circuitry to receive the first and second performance rating signals and control a setting for a body bias signal for the first domain and control a setting for a body bias signal for the second domain responsive to the performance rating signals. In some embodiments, the control circuitry also provides supply voltage signals and clock signals responsive to the performance signals. The first and second domains may have clock signals with the same frequency and the bias values are set such that the transistors of the first and second domains can switch properly while the first and second domains have the clock signals and wherein one of the first and second domains operates at less than optimal performance.

Dependencies are inferred from the claim text.