Minimum memory implementation of high speed viterbi decoder
AssigneeTexas Instruments Incorporated
InventorHirohisa Yamaguchi
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AssigneeTexas Instruments Incorporated
InventorHirohisa Yamaguchi
Estimating the term…
A Viterbi decoder is disclosed that utilizes minimum memory for the decoding operation. A plurality of FIFOs are provided which are divided into two blocks of FIFOS, one for upper states and one for lower states. The operations are calculated utilizing previously stored branch metrics and then determining the new branch metric by retrieving information from the FIFOs, adding the new branch metric defined with the soft decision table and then selecting the most likely path therefrom, and discarding the other. This new branch metric is then stored back into the FIFOs to replace the old. Each branch metric calculation results in a determination of the most likely path for that state and also the decoded data bit for a given state associated with a received symbol. This is stored in a separate memory for each of the nodes, and thereafter, the output is decoded to retrieve the decoded bit stream.
A method for decoding an encoded data sequence with a Viterbi algorithm, wherein convolutionally encoded symbols are transmitted and received, comprising the steps of:
A method for decoding a decoded data sequence wherein convolutionally encoded symbols are transmitted and received, comprising the steps of:
A decoder for decoding an encoded data sequence with a Viterbi algorithm, wherein convolutionally encoded symbols are transmitted and received, comprising:
A decoder for decoding a decoded data sequence wherein convolutionally encoded symbols are transmitted and received, comprising:
Dependencies are inferred from the claim text.