Semiconductor integrated circuit including test facilitation circuit and test method thereof
AssigneeKawasaki Steel Corporation
InventorMasayuki Yoshiyama
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit and method of use improve a rate of defect detection and also facilitate production of test patterns while suppressing an increase of the circuit area. The semiconductor integrated circuit includes a plurality of pairs of a sequence circuit and selector circuit. Each of the sequence circuits stores an operation result of an internal circuit, whereas each selector circuit is responsive to a control signal for selecting one of the data stored in its associated sequence circuit and an inverted version of the data to thereby output the selected data. A control circuit operates to count up or divide clocks and then control the selector circuits constituting the plurality of pairs in accordance with the resultant count values.
Claims20
A semiconductor integrated circuit comprising:
- a plurality of unit test circuits;
- said unit test circuits including a pair of a sequence circuit and a selector circuit, the sequence circuit storing therein an operation result of an internal circuit, the selector circuit being responsive to a control signal which selects one of two execution modes of a standard mode and an inversion mode for selecting and outputting one of data stored in the sequence circuit and an inverted version of the data;
- and
- a control circuit for generation of the control signal to be supplied to said selector circuit.
A semiconductor integrated circuit including a plurality of input terminals, a plurality of output terminals, a random logical circuit composed of a combination circuit, and a plurality of flip-flops and/or latches, characterized by further including:
- a selector circuit provided in a way corresponding to each of part or all of the flip-flops or latches of said plurality of flip-flops and/or latches, for selecting and outputting one of the data stored in a corresponding flip-flop or latch and an inverted output data of the data in response to a control signal as supplied from a control circuit;
- and the control circuit for generating the control signal to be supplied to said selector circuit.
A test method for use with a semiconductor integrated circuit including a plurality of input terminals, a plurality of output terminals, a random logical circuit comprising a combination circuit, and a plurality of flip-flops and/or latches, the semiconductor integrated circuit further including a selector circuit provided in correspondingly to each of part or all of flip-flops or latches of said plurality of flip-flops and/or latches for selecting and outputting any one of data stored in a corresponding flip-flop or latch and an inverted version of the data in response to a control signal being supplied from a control circuit, and the control circuit for generating the control signal to be supplied to said selector circuit, characterized by letting the semiconductor integrated circuit execute an operation including a control operation of the selector circuit by said control circuit.
Dependencies are inferred from the claim text.