Fast scannable output latch with domino logic input
AssigneeInternational Business Machines Corporation
InventorPeter Thomas Freiburger
Life of this patent
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Abstract
A scannable fast domino output latch is provided. A scannable latch circuit includes a scan logic receiving a scan data input and a scan data clock. The scannable latch circuit includes a transistor stack receiving a data input and receiving a system clock. A first inverter is connected to the transistor stack. The first inverter provides a latch output. A feedback path logic is connected across the first inverter. The feedback path logic is activated responsive to both the system clock and the scan data clock. Improved performance is provided by eliminating the transfer gate and active feedback from the critical path of the scannable latch circuit. The feedback path logic is activated when both the system clock and the scan data clock are low.
Claims12
A scannable latch circuit comprising:
- a scan logic receiving a scan data input and a scan data clock;
- a data input;
- a transistor stack receiving said data input and receiving a system clock;
- a first inverter connected to said transistor stack and providing a latch output;
- a feedback path logic connected across said first inverter;
- said feedback path logic being activated responsive to both said system clock and said scan data clock.
A scannable latch circuit comprising:
- a scan logic receiving a scan data input and a scan data clock;
- a data input;
- a Domino logic transistor stack receiving said data input and receiving a system clock;
- a first inverter connected to said transistor stack and providing a latch output;
- a feedback path logic connected across said first inverter;
- said feedback path logic being activated responsive to both said system clock and said scan data clock.
Dependencies are inferred from the claim text.