Method and apparatus for built-in self-test of logic circuitry

A system having a plurality of logic circuits fabricated on a plurality of chips within the system, comprising:

• logic under test fabricated on a chip of the system, the logic under test having a plurality of test points, each test point having a plurality of nodes;
• a linear finite state machine (LFSM) having subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine, the contents of the linear state machine being readable from or writable to the logic under test via scan, the linear finite state machine being fabricated on the same chip and of the same technology as the logic under test;
• and
• a test data bus coupled between the logic under test and the linear firite state machine, the test data bus configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.

A method for fabricating a chip having built-in self-test (BIST) capability, comprising:

• fabricating logic under test on the chip, the logic under test having a plurality of test points, each test point having a plurality of nodes;
• providing a linear finite state machine (LFSM) on the chip and of the same technology as the logic under test, the linear finite state machine having subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine, the contents of the linear state machine being readable or writable via scan;
• and
• providing a test data bus coupled between the logic under test and the linear finite state machine, including configuring the test data bus to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.

A method for using a chip having built-in self-test (BIST) capability, comprising:

• controlling an operation of logic under test, the logic under test having a plurality of test points, each test point having a plurality of nodes;
• generating non-sequential, pseudorandom binary numbers using a linear finite state machine (LFSM), including generating the non-sequential, pseudorandom binary numbers that are stochastically determined by a characteristic polynomial of the linear finite state machine;
• selectably reading or writing the contents of the linear finite state machine via scan;
• and
• conveying data, in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points, over a test data bus coupled between the logic under test and the linear finite state machine.