US 6,272,651 B1 · System and method for improving processor read latency in a system employing error checking and correction

Abstract

A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol. Also, all bus master devices (CPUs) on the processor bus may perform the same data integrity protocol. When a CPU requests read data from main memory, the bus interface unit forwards the read data and error information unmodified to the processor bus bypassing the data integrity logic within the system interface unit. However, the system interface unit may still perform the data integrity protocol in parallel with the requesting CPU so that the system interface unit may track errors and possibly notify the operating system or other error control software of any errors. In this manner processor read latency is improved without sacrificing data integrity. Furthermore, the system interface unit may still track errors on processor reads. If the read request is from a device on a peripheral bus (AGP or PCI bus), then the system interface unit performs the data integrity protocol on the data and error bits before forwarding the read data to the appropriate bus.

Claims19

Dependent claims

A computer, comprising:

at least one processor coupled to a processor bus, said processor having data integrity logic for performing a data integrity protocol;
main memory;
a system interface unit having error logic for performing said data integrity protocol on read data and error information received from said main memory without passing on said processor bus, wherein said system interface unit is coupled to said processor bus, said main memory, and a first peripheral bus, and wherein said system interface unit is configured to pass read data and error information from said main memory to said processor bus without passing through said error logic and to pass read data and error information from said main memory to said first peripheral bus through said error logic;
and
a hard drive coupled to said first peripheral bus.

2 more elements

Dependencies are inferred from the claim text.

System and method for improving processor read latency in a system employing error checking and correction

Life of this patent

System and method for improving processor read latency in a system employing error checking and correction

Life of this patent

Abstract

Claims19