Programmable logic device having an integrated phase lock loop
AssigneeCypress Semiconductor Corporation
InventorsKrishna Rangasayee, John Shannon
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Abstract
The present invention integrates a phase lock loop (PLL) with a programmable logic device (PLD) to realize a flexible PLD with a variety of clocking options. The present invention generates multiple clock frequencies internally to a programmable logic device using a single reference clock input. The programmer can dynamically change the functionality of the programmable logic device. As a result, a “virtual hardware device” is realized. The ability to change the frequency of operation also dynamically offers a tremendous advantage to users of reconfigurable computing.
Claims20
A device comprising:
- a programmable logic circuit configured to (i) generate one or more control signals and (ii) receive one or more clock signals;
- and
- a phase lock loop circuit configured to generate said one or more clock signals, each capable of oscillating at a different one of a plurality of frequencies, said clock signals generated in response to (i) a reference clocks (ii) said one or more control signals, and (iii) one or more of said clock signals wherein said programmable logic circuit and said phase lock loop circuit are integrated on a single circuit.
A method for dynamically changing a frequency of operation of a programmable logic circuit comprising the steps of:
- (a) configuring said programmable logic circuit to generate one or more control signals and receive one or more clock signals;
- and
- (b) generating said one or more clock signals with a phase lock loop circuit, each of said one or more clock signals being:
- (i) capable of oscillating at a different one of a plurality of frequencies, and
- (ii) generated in response to a reference clock, one or more of said clock signals, and said one or more control signals.
A device comprising:
- means for implementing programmable logic for manipulating information to generate one or more control signals, wherein said means for implementing programmable logic receives one or more clock signals;
- and
- means for generating said one or more clock signals in response to (i) a reference clock, (ii) said one or more control signals, and (iii) one or more of said clock signals wherein said one or more clock signals are each capable of oscillating at a different one of a plurality of frequencies, said means for implementing programmable logic and said means for generating are integrated on a single circuit.
Dependencies are inferred from the claim text.