Method of and circuit for instruction/data prefetching using non-referenced prefetch cache

An instruction prefetching circuit comprising:

• a central processing unit for outputting various control signals required for the execution of a program requiring a memory reference;
• a lower memory for storing instruction blocks required for the execution of the program by the central processing unit;
• a prefetch control unit for controlling a prefetch of instruction blocks to be referenced by the central processing unit;
• a prefetch buffer for temporarily storing instruction blocks prefetched from the lower memory and outputting control signals respectively on the basis of whether the stored instruction blocks have been referenced by the central processing unit;
• a demultiplexor for demultiplexing instruction blocks outputted from the prefetch buffer into those referenced by the central processing unit and those not referenced by the central processing unit respectively on the basis of the control signals outputted from the prefetch buffer;
• a non-referenced prefetch block storing unit for storing those, not referenced by the central processing unit, of the instruction blocks outputted from the demultiplexor;
• and
• an instruction cache for storing the instruction blocks outputted from the lower memory, the instruction blocks outputted from the demultiplexor and instruction blocks outputted from the non-referenced prefetch block storing unit.

A data prefetching circuit comprising:

• a central processing unit for outputting various control signals required for the execution of a program requiring a memory reference;
• a lower memory for storing data blocks required for the execution of the program by the central processing unit;
• a prefetch control unit for controlling a prefetch of data blocks to be referenced by the central processing unit;
• a prefetch buffer for temporarily storing data blocks prefetched from the lower memory and outputting control signals respectively on the basis of whether the stored data blocks have been referenced by the central processing unit;
• a demultiplexor for demultiplexing data blocks outputted from the prefetch buffer into those referenced by the central processing unit and those not referenced by the central processing unit respectively on the basis of the control signals outputted from the prefetch buffer;
• a non-referenced prefetch block storing unit for storing those, not referenced by the central processing unit, of the data blocks outputted from the demultiplexor;
• and
• a data cache for storing the data blocks outputted from the lower memory, the data blocks outputted from the demultiplexor and data blocks outputted from the non-referenced prefetch block storing unit.

A circuit for prefetching information stored in a memory device for use by a central processing unit (CPU), comprising:

• a first memory that stores information accessed from the memory for use by the CPU;
• a second memory that stores prefetched information to be used by the CPU and that stores control information indicative of whether the prefetched information has been accessed by the CPU;
• a third memory that stores prefetched information which has been unused by the CPU, wherein the unused information stored in said third storage device is accessible by the CPU;
• means, coupled to at least one of said first memory and said second and third memories, for transferring prefetched information unused by the CPU from said second memory to said third memory based on the control information;
• and
• a control circuit that controls operations of said first, second and third memories.