Synchronization and control system for an arrayed processing engine

A method for synchronously controlling a processing engine adapted to process transient data, the method comprising the steps of:

• symmetrically arraying a plurality of processing elements as pipeline rows and columns, each row comprising processing element stages of a pipeline that sequentially execute operations on the transient data and each column comprising processing elements that operate in parallel to perform substantially the same operation on the transient data;
• and
• controlling the processing element stages (i) of each pipeline row to ensure completion of processing of current transient data by each stage prior to loading new transient data into the stages at a new phase and (ii) of each column to ensure that each stage performs its processing at a shifted phase with respect to the other columned stages, the pipeline rows and columns controlled by input sequencing circuitry of an input header buffer (IHB).

Apparatus for synchronously controlling a processing engine adapted to process transient data, the method comprising the steps of:

• means for symmetrically arraying a plurality of processing elements as pipeline rows and columns, each row comprising processing element stages of a pipeline that sequentially execute operations on the transient data and each column comprising processing elements that operate in parallel to perform substantially the same operation on the transient data;
• and
• means for controlling the processing element stages (i) of each pipeline row to ensure completion of processing of current transient data by each stage prior to loading new transient data into the stages at a new phase and (ii) of each column to ensure that each stage performs its processing at a shifted phase with respect to the other columned stages.