Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

A central processing unit comprising:

• an instruction register having a predetermined bit length;
• an instruction decoder;
• and
• an execution unit,
• wherein the instruction register is capable of fetching two instructions from an instruction memory in a single instruction fetch operation, each instruction having half the bit length of the predetermined bit length of the instruction register,
• wherein the instruction decoder is coupled to the instruction register and decodes a selected instruction from the instruction register and supplies control signals to the execution unit corresponding to the result of the decoding instruction;
• and
• wherein the execution unit receives the control signals and executes an operation based on the control signals.