Pipelined memory controller
AssigneeMicron Electronics, Inc.
InventorJoseph Jeddeloh
Life of this patent
Estimating the term…
Abstract
A memory controller which has multiple stages of pipelining. A request buffer is used to hold the memory request from the processor and peripheral devices. The request buffer comprises a set of rotational registers that holds the address, the type of transfer and the count for each request. The pipeline includes a decode stage, a memory address stage, and a data transfer stage. Each stage of the pipeline has a pointer to the request buffer. As each stage completes its processing, a state machine updates the pointer for each of the stages to reference a new memory request which needs to be processed.
Claims21
A computer system, comprising:
- a memory module which stores digital information;
- and
- a memory controller, connected to the memory module comprising:
- a request buffer which receives and stores multiple memory requests,
- a decode module having a pointer to the request buffer,
- an addressing module having a pointer to the request buffer,
- a data transfer module having a pointer to the request buffer, and
- a state machine which updates the pointer in the decode module, the addressing module and the data transfer module.
A system for handling a at least one memory request, comprising:
- a pipeline processor for processing the at least one memory request in a plurality, of stages, wherein in a first stage, the at least one memory request for digital information;
- is received and stored in a request buffer, wherein in a second stage the at least one memory request is decoded, wherein in a third stage the at least one memory request is sent to a memory module, and wherein in a fourth stage the data from the at least one memory request is received from the memory module.
A memory controller, comprising:
- a request buffer which receives and stores multiple memory requests;
- decode module including a pointer to the request buffer;
- an addressing module including a pointer to the request buffer;
- a data transfer module including a pointer to the request buffer;
- and
- a state machine which updates the pointer in the decode module, the addressing module and the data transfer module.
A computer system, comprising:
- a processor;
- a processor bus connected to the processor;
- a memory module;
- a memory controller connected to the processor bus and the memory module, wherein the memory controller is responsive to memory requests from the processor, and wherein the memory controller comprises:
- at least one rotational register configured to receive memory requests from the processor through the processor bus,
- a decode module having a pointer referencing one of said at least one rotational register,
- an addressing module having a pointer referencing one of said at least one rotational register,
- a data transfer module having a pointer referencing one of said at least one rotational register, and
- a state machine which updates the pointer in the decode module the addressing module and the data transfer module;
- and
- a memory bus having address, data, and clock portions and connected between the memory device and the memory controller, wherein the memory bus transfers address, data and clock signals between the memory device and the memory controller.
Dependencies are inferred from the claim text.