Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals

An integrated synchronous memory device having a read latency and write latency of N, where N is a positive real number, the memory device being operative to accept a read command within a latency period following a write command, comprising:

• a memory array;
• an address input terminal;
• an address path between the address input terminal and the memory array, the address path including an interim address register operable to store an address corresponding to the write command;
• an input data path, including an interim data register coupled to the memory array, the interim data register being operable to store a set of write data corresponding to the write command;
• and
• a look-ahead circuit configured to detect an upcoming available write interval at the memory array following the read command, the look-ahead circuit being configured to activate the interim data register and the interim address register in response to the detected upcoming available write interval, to provide the stored write address from the interim address register and the stored set of write data from the interim data register to the memory array.