Contingent response apparatus and method for maintaining cache coherency

A contingent response arrangement for a first processor which shares a pipelined address bus with at least one other processor, the contingent response arrangement comprising:

• (a) a pending operation queue having a plurality of pending operation queue locations, each pending operation queue location for storing an address for a first processor operation pending on the pipelined address bus;
• (b) a pending operation queue comparator arrangement (i) for receiving a snoop address from another processor sharing the pipelined address bus, and (ii) for comparing the received snoop address with the address stored in each pending operation queue location to identify a matched operation, the matched operation comprising a first processor operation which is pending on the pipelined address bus and which specifies an address which matches the snoop address;
• (c) a snoop pipeline having a plurality of pipeline stages, each pipeline stage including at least one contingent response flag location and an identifier location, each contingent response flag location included in a pipeline stage for storing a contingent response flag and the identifier location of each pipeline stage for storing an identifier associated with a particular matched operation;
• and
• (d) a contingent response flag control arrangement associated with the snoop pipeline, the contingent response flag control arrangement (i) for setting a contingent response flag at one of the contingent response locations in a first snoop pipeline stage in response to the matched operation identified by the pending operation comparator arrangement, and (ii) for clearing the response flag of any critical snoop pipeline stage which contains an identifier which matches an identifier for an unsuccessful finishing operation from the first processor.

A method for providing a contingent response from a first processor which shares a pipelined address bus with at least one other processor, the method comprising the steps of:

• (a) identifying a matched operation, the matched operation comprising a first processor operation which is pending on the pipelined address bus and which specifies an address which matches a snoop address;
• (b) storing a contingent response flag and an operation identifier in a contingent response storage arrangement in response to the matched operation, the operation identifier identifying the matched operation;
• (c) where the operation identifier is matched by an identifier for an unsuccessful finishing operation during a critical period, clearing the contingent response flag associated with the matched identifier;
• and
• (d) where the operation identifier is not matched by the identifier for an unsuccessful finishing operation during a critical period, using the contingent response flag to signal a response to a bus operation associated with the snoop address.

A data processing system comprising:

• (a) a plurality of processors which each share a pipelined address bus;
• (b) a plurality of pending operation units, each different pending operation unit associated with a different one of the processors for identifying a matched operation from the respective processor, the matched operation comprising an operation from the respective processor which is pending on the pipelined address bus and which specifies an address which matches a snoop address;
• (c) a plurality of snoop pipelines, each different snoop pipeline being associated with a different one of the processors and having a plurality of pipeline stages, each pipeline stage including a contingent response flag location and an identifier location, each contingent response flag location for storing a contingent response flag and each identifier location for storing an identifier associated with a particular matched operation;
• and
• (d) a different contingent response flag control arrangement associated with each different snoop pipeline, the respective contingent response flag control arrangement (i) for setting the response flag in one snoop pipeline stage of the respective snoop pipeline in response to the matched operation identified by the pending operation unit and (ii) for clearing the response flag of any critical snoop pipeline stage of the respective snoop pipeline which contains an identifier which matches an identifier for an unsuccessful finishing operation from the respective processor.