Cache coherency protocol having hovering (H), recent (R), and tagged (T) states

A method of maintaining cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said method comprising:

• in a first cache among said plurality of caches, storing a first data item in association with an address tag indicating an address of said first data item and setting a coherency indicator in said first cache to a first state that indicates that said address tag is valid and that said first data item is invalid in said first cache;
• in response to said first cache receiving a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, said data transfer including a second data item that is modified with respect to a corresponding data item in said system memory, storing said second data item in said first cache in association with said address tag in place of said first data item and updating said coherency indicator to a second state indicating that said second data item is valid and modified with respect to said corresponding data item in system memory and that said first cache is responsible, among all of said plurality of caches, for writing back said second data item to said system memory;
• and
• writing back said second data item from said first cache to said system memory only in response to deallocation by said first cache of a cache line containing said second data item while said coherency indicator is set to said second state.

A cache for supporting cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said cache comprising:

• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, said first state indicating that said address tag is valid and that said first data item is invalid;
• and
• means, responsive to receiving a data transfer from said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, said data transfer being initiated by another of said plurality of caches and including a second data item that is modified with respect to a corresponding data item in said system memory, for storing said second data item in said cache in association with said address tag and for updating said coherency indicator to a second state indicating that said second data item is valid and that said cache is responsible for writing back said second data item to said system memory.

A cache for supporting cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said cache comprising:

• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, said first state indicating that said address tag is valid and that said first data item is invalid;
• means, responsive to receiving a data transfer from said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, said data transfer being initiated by another of said plurality of caches and including a second data item that is modified with respect to a corresponding data item in said system memory, for storing said second data item in said cache in association with said address tag and for updating said coherency indicator to a second state indicating that said second data item is valid and that said cache is responsible for writing back said second data item to said system memory;
• and
• means, responsive only to deallocation by said cache of a cache line containing said second data item while said coherency indicator is set to said second state, for writing said second data item from said cache to said system memory.

A data processing system, comprising:

• an interconnect;
• a plurality of processors;
• a plurality of caches coupled to said plurality of processor and to said interconnect, wherein a first cache among said plurality of caches includes:
• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, wherein said first state indicates that said address tag is valid and that said first data item is invalid;
• and
• means, responsive to receiving a data transfer from said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, said data transfer being initiated by another of said plurality of caches and including a second data item that is modified with respect to a corresponding data item in said system memory, for storing said second data item in said first cache in association with said address tag and for updating said coherency indicator to a second state indicating that said second data item is valid and that said first cache is responsible for writing back said second data item to said system memory.

A data processing system, comprising:

• an interconnect;
• a plurality of processors;
• a plurality of caches coupled to said plurality of processor and to said interconnect, wherein a first cache among said plurality of caches includes:
• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, wherein said first state indicates that said address tag is valid and that said first data item is invalid;
• and
• means, responsive to receiving a data transfer from said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, said data transfer being initiated by another of said plurality of caches and including a second data item that is modified with respect to a corresponding data item in said system memory, for storing said second data item in said first cache in association with said address tag and for updating said coherency indicator to a second state indicating that said second data item is valid and that said first cache is responsible for writing back said second data item to said system memory;
• and
• means, responsive only to deallocation by said first cache of a cache line containing said second data item while said coherency indicator is set to said second state, for writing said second data item from said first cache to said system memory.