Cache structure and method for improving worst case execution time
AssigneeLucent Technologies Inc.
InventorG. N. Prasanna
Life of this patent
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Abstract
An apparatus and method using selectively controlled cache/no-cache bits for improving the real-time performance of applications run on computers having cache memory by controlling the caching of different regions of address space thereby reducing thrashing or other forms of interference in the cache memory and improving the WCET performance of such applications.
Claims17
A cache structure for improving the worst case-execution time (WCET) of applications run on a computer having a cache memory, comprising:
- at least one cache/no-cache bit assigned to each block of data and instructions, whereby using an integer linear programming (ILP) algorithm the combination of cache/no-cache bit settings for each block of data and instructions which result in reduced thrashing and a desired WCET for the application can be determined so that these settings can be used thereafter to improve the real-time performance of the application, wherein the ILP algorithm identifies address patterns causing thrashing in the cache memory.
A cache structure for improving the worst case-execution time (WCET) of applications run on a computer having a cache memory, comprising:
- at least one cache/no-cache bit assigned to each block of data and instructions, whereby using an ILP algorithm the combination of cache/no-cache bit settings for each block of data and instructions which result in reduced thrashing between two data blocks in the cache memory and thus a desired WCET for the application can be determined so that these settings can be used thereafter to improve the real-time performance of the application, wherein the ILP algorithm identifies an address pattern causing thrashing in the cache memory.
A method for improving the WCET of applications run on a computer having a cache memory, comprising the steps of:
- assigning at least one cache/no-cache bit to each block of data and instructions;
- utilizing ILP to determine which combination of cache/no-cache bit settings for each block of data and instructions result in a desired WCET for the application, wherein the ILP identifies an address pattern causing thrashing in the cache memory;
- and
- using the cache/no-cache bit settings providing the desired result thereafter to improve the real-time performance of the application.
Dependencies are inferred from the claim text.