Data processor

A data processor comprising:

• an instruction address generator;
• a cache memory having entries each storing an instruction address and instruction corresponding to the instruction address;
• an instruction decoder decoding an instruction from said cache memory or another memory corresponding to an instruction address from said instruction address genmerator;
• and
• an address transformation circuit transforming a logical address generated by said instruction address generator to a physical address;
• wherein the data processor issues an instruction that makes entries in said cache memory ineffective.

A data processor comprising:

• an instruction address generator;
• a cache memory having entries each storing an instruction address and instruction corresponding to the instruction address;
• an instruction decoder decoding an instruction from said cache memory or another memory corresponding to an instruction address from said instruction address generator;
• and
• an address transformation circuit transforming a logical address generated by said instruction address generator to a physical address;
• wherein the data processor executes an instruction that makes entries in said cache memory ineffective.

A data processor comprising:

• an instruction address generator;
• a cache memory;
• an instruction decoder decoding an instruction from said cache memory or another memory corresponding to an instruction address from said instruction address generator;
• and
• an address transformation circuit transforming a logical address generated by said instruction address generator to a physical address;
• wherein the data processor issues an instruction that makes said cache memory ineffective.

A data processor comprising:

• an instruction address generator;
• a cache memory;
• an instruction decoder decoding an instruction from said cache memory or another memory corresponding to an instruction address from said instruction address generator;
• and
• an address transformation circuit transforming a logical address generated by said instruction address generator to a physical address;
• wherein the data processor executes an instruction that makes entries said cache memory ineffective.