N-way set-associative cache memory which includes a store hit buffer for improved data access
AssigneeIntel Corporation
InventorsEitan Rosen, Jack Doweck
Life of this patent
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Abstract
A cache memory circuit is disclosed that includes a store hit buffer that buffers write operations to the cache memory circuit and that removes write operations from the critical speed path for the cache memory array. The store hit buffer includes circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer and circuitry for merging the write operation from the store hit buffer with the read operation.
Claims12
An N-way, set associative cache memory comprising:
- a memory array having N sets of data bit lines and N sets of associated address tag bit lines;
- an addressing circuit which generates a tag compare address and a set address for a read operation, and write control signals for a write operation;
- N amplifier circuits, each of which is coupled to corresponding sets of the data/address tag bit lines of the memory array, each of the N amplifier circuits having outputs which provide data and address tags sensed from the respective data/address tag bit lines of the memory array;
- N read/write (R/W) circuits, each of which is correspondingly coupled to the outputs of the N amplifier circuits and also to the addressing circuit, each of the R/W circuits comprising:
- a buffer circuit for buffering write data/address information preceding a write operation, the buffer circuit including a comparator which generates a set compare result when the set address matches the write address;
- comparator means for comparing the address tags sensed by the N amplifier circuits with the tag compare address to produce a match signal;
- and
- multiplexer means controlled by the set compare result and match signal for selecting as a cache output either a write data bit from the buffer circuit or a data bit sensed from the memory array.
A computer system comprising:
- a processor;
- data and address buses coupled to the processor;
- an N-way, set associative cache memory coupled to the processor via the data and address buses, the cache memory comprising:
- a memory array having N sets of data bit lines and N sets of associated address tag bit lines;
- an addressing circuit coupled to the address bus, the addressing circuit generating a tag compare address and a set address for a read operation by the processor, and write control signals for a write operation by the processor;
- N amplifier circuits, each of which is coupled to corresponding sets of the data/address tag bit lines of the memory array, each of the N amplifier circuits having outputs which provide data and address tags sensed from the respective data/address tag bit lines of the memory array;
- N read/write (R/W) circuits, each of which is correspondingly coupled to the outputs of the N amplifier circuits and also to the addressing circuit, each of the R/W circuits comprising:
- a buffer circuit for buffering write data/address information preceding a write operation, the buffer circuit including a comparator which generates a set compare result when the set address matches the write address;
- comparator means for comparing the address tags sensed by the N amplifier circuits with the tag compare address to produce a match signal;
- and
- multiplexer means controlled by the set compare result and match signal for selecting as a cache output either a write data bit from the buffer circuit or a data bit sensed from the memory array.
In a computer system which includes a processor which performs memory transactions that include a write operation for writing data to an N-way, set associative cache memory, and a read operation for reading data from the cache memory, a method of performing such a memory transaction comprising the steps of:
- generating a tag compare address and a set address for the read operation, and write control signals which select one of the N ways for the write operation;
- sensing data and address tags from the associated bit lines of a memory array in the cache memory;
- buffering write data/address information preceding the write operation;
- generating a set compare result when the set address matches the write address;
- comparing the sensed address tags with the tag compare address to produce a match signal;
- and
- selecting as an output either a write data bit from the buffer circuit or a data bit sensed from the memory array.
Dependencies are inferred from the claim text.