Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system

A bus arbiter for a computer system, comprising:

• a low priority arbitration ring having a plurality of low priority ports assigned to respective low priority peripheral devices;
• a high priority arbitration ring having a plurality of high priority ports assigned to respective high priority peripheral devices and to a first one of the low priority peripheral devices elevated from the low priority ports during times in which data transfers to or from said first one of the low priority peripheral devices are interrupted;
• and
• a low priority pointer which points to one of the low priority ports for prioritizing requests from among the low priority peripheral devices based on their proximity to the pointed-to low priority slot.

A computer, comprising:

• a microprocessor;
• a plurality of high and low priority peripheral devices, at least one of which is coupled to a printed circuit board separate from another printed circuit board on which the microprocessor resides;
• an arbiter coupled to a peripheral bus on which the plurality of high and low priority peripheral devices are operably coupled, the arbiter comprising:
• a high priority arbitration ring having a plurality of high priority ports assigned to the plurality of high priority peripheral devices;
• a low priority arbitration ring having a plurality of low priority ports assigned to the plurality of low priority peripheral devices;
• wherein one of the low priority peripheral devices is assigned to one of the plurality of high priority ports and is granted mastership of the peripheral bus before any other of the low priority peripheral devices whenever a data transfer to or from said one of the plurality of low priority peripheral devices is retried;
• and;
• a high priority pointer which points to one of the high priority ports for prioritizing requests from among the high priority peripheral devices based on their proximity to the pointed-to high priority port.

A computer, comprising:

• a microprocessor;
• a plurality of high and low priority peripheral devices, at least one of which is coupled to a printed circuit board separate from another printed circuit board on which the microprocessor resides;
• an arbiter coupled to a peripheral bus on which the plurality of high and low priority peripheral devices are operably coupled, the arbiter comprising:
• a high priority arbitration ring having a plurality of high priority ports assigned to the plurality of high priority peripheral devices;
• a low priority arbitration ring having a plurality of low priority ports assigned to the plurality of low priority peripheral devices;
• wherein one of the low priority peripheral devices is assigned to one of the plurality of high priority ports and is granted mastership of the peripheral bus before any other of the low priority peripheral devices whenever a data transfer to or from said one of the plurality of low priority peripheral devices is retried;
• and;
• a low priority pointer which points to one of the low priority ports for prioritizing requests from among the low priority peripheral devices based on their proximity to the pointed-to low priority port.