Microprocessor architecture capable of supporting multiple heterogeneous processors

A method of transferring data in a multiprocessor architecture capable of supporting multiple processors comprising the steps of:

• providing a dynamic priority to input/output unit (IOU), D-cache and I-cache device requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption;
• keeping track of the number of times each of said factors occurs;
• and
• changing the priority of said devices as a function of said intrinsic priority and said number.

In a computer system having a memory array unit (MAU), a plurality of memory ports to provide access to said MAU, and a plurality of devices which access said MAU via said memory ports, a system for arbitrating for said memory ports, comprising:

• a priority assignor to assign priorities to the devices, comprising
• an initial priority assignor to assign an initial priority to each of said devices,
• a first priority increaser to increase a priority associated with a first device having an initial priority less than a first priority value if said first device is repeatedly denied service to a memory port,
• a priority decreaser to decrease a priority associated with a second device having an initial priority greater than a second priority value if it is determined that said second device is repeatedly granted service to a memory port, and
• a second priority increaser to increase a priority associated with a third device if a row addressed by a pending memory access request issued by said third device matches a row addressed by a preceding memory access request last serviced by said MAU;
• and
• a request servicer to service requests for the memory ports issued by the devices in accordance with said priorities.

In a computer system having a memory array unit (MAU), a plurality of memory ports to provide access to said MAU, and a plurality of devices which access said MAU via said memory ports, a method for arbitrating for said memory ports, comprising the steps of:

• (1) assigning priorities to said devices;
• and
• (2) servicing requests for said memory ports issued by said devices in accordance with said priorities;
• wherein step (1) comprises the steps of:
• (a) assigning an initial priority to each of said devices;
• (b) increasing a priority associated with a first device having an initial priority less than a first priority value if said first device is repeatedly denied service to a memory port;
• (c) decreasing a priority associated with a second device having an initial priority greater than a second priority value if it is determined that said second device is repeatedly granted service to a memory port;
• and
• (d) increasing a priority associated with a third device if a row addressed by a pending memory access request issued by said third device matches a row addressed by a preceding memory access request last serviced by said MAU.