Efficient data transfer mechanism for input/output devices

A controller for transferring data between a host system and external devices the host system having memory with data buffers, a descriptor queue and a receive status queue, the controller comprising:

• a first register that maintains a number of descriptors that are currently available in the descriptor queue for use in a direct memory access (DMA) transfer;
• a second register that maintains an address of the location of the first descriptor of the currently available descriptors in the descriptor queue;
• a buffer for temporarily storing currently available descriptors that are obtained from the descriptor queue;
• and
• hardware circuitry that controls obtaining the currently available descriptors from the descriptor queue for temporary storage in the buffer, the circuitry retrieving as many currently available descriptors as possible to fill the buffer, based on the number in the first register and the address in the second register.