Filter device

A filter device comprising a shift register, a plurality of memories connected to this shift register and increased in the bit width of input address by one bit each, and a selector for selecting outputs from these plurality of memories,

• wherein said shift register output is used as a higher side address of each one of said memories, a lower side address of each one of said memory addresses is common, the bit width of the higher side address increases by one bit each starting from one bit, addresses are assigned sequentially from the lower side of the higher side address of said memories depending on the shift from the highest side bit of said shift register, and the memory outputs are changed over by the selector depending on the bit position of the shift register of the final bit before stop of transmission.

A filter device comprising a shift register, an inverter for inverting the bits except for the highest bit of the output signal from this shift register from 1 to 0 or from 0 to 1, a first selector for selecting the bits except for the highest bit of this inverter output or said shift register output, a memory using the output of this first selector as the higher side input address, an operating circuit for operating this memory output, and a second selector for selecting and issuing either this operating circuit output or said memory output,

• wherein when the highest bit of said shift register is 1, the first selector selects said inverter output and the second selector selects said operating circuit output, and when the highest bit of said shift register is 0, the first selector selects said shift register output and the second selector selects said memory output.

A filter device comprising a shift register, an inverter for inverting the bits except for the highest bit of the output signal from this shift register from 1 to 0 or from 0 to 1, a first selector for selecting the bits except for the highest bit of this inverter output or said shift register output, a memory using the output of this first selector as the higher side input address, an operating circuit for operating this memory output, and a second selector for selecting and issuing either this operating circuit output or said memory output,

• wherein when the highest bit of said shift register is 0, the first selector selects said inverter output and the second selector selects said operating circuit output, and when the highest bit of said shift register is 1, the first selector selects said shift register output and the second selector selects said memory output.