Programmable and expandable fuzzy processor for pattern recognition

A fuzzy processor for operating with a plurality of standard patterns each having a plurality of features, said fuzzy processor comprising:

• a membership function I/O circuit for inputting and outputting a plurality of membership functions respectively corresponding to each one of said plurality of features of each one of said plurality of standard patterns;
• a feature decoder for receiving a to-be-recognized pattern having a plurality of input features, and generating a plurality of feature values;
• a plurality of membership function memory units respectively corresponding to each one of said plurality of features of each one of said plurality of standard patterns for storing said plurality of membership functions and addressed by said plurality of feature values to generate a plurality of membership degrees for said plurality of input features corresponding to said plurality of standard patterns, respectively;
• a plurality of current-type digital/analog converters corresponding to said plurality of standard patterns respectively for receiving said plurality of membership degrees and generating a plurality of current-type membership degrees;
• a plurality of accumulators corresponding to said plurality of converters for receiving said plurality of current-type membership degrees and generating a plurality of synthesis membership degrees;
• and
• an expandable synthesis membership degree comparing circuit including:
• an input circuit unit having a plurality of inputs for receiving a plurality of currents representing said plurality of synthesis membership degrees and having a plurality of outputs for outputting at least one of said plurality of currents;
• a winner-take-all (WTA) circuit unit receiving said plurality of currents from said input circuit for establishing a plurality of representing voltages corresponding thereto wherein the maximum one among said plurality of representing voltages generates a representing current controlled by a control terminal to be output on a VO terminal, and generating a plurality of first voltage output signals respectively corresponding to the received plurality of currents for indicating said maximum current;
• and
• a feedback control and voltage output unit having a clock terminal for receiving a clock signal, receiving said plurality of first voltage output signals from said winner-take-all circuit unit, generating a plurality of feedback control signals according to said plurality of first voltage output signals in one operation cycle controlled by said clock signal to control the outputs of said input circuit unit wherein one of said plurality of feedback control signals corresponding to the first voltage output signal indicative said maximum current is set inactive for guiding said input circuit unit to clear a corresponding input current, and converting said plurality of first voltage output signals to a plurality of second voltage output signals on said plurality of outputs in said operation cycle;
• a reset terminal being provided for receiving reset signals to reset said feedback control and voltage output unit.