US 6,272,453 B1 · Concurrent legacy and native code execution techniques

Abstract

A method and apparatus for emulating instructions of a microprocessor (“legacy instructions”) with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of “thunk” objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.

Claims10

Dependent claims

An apparatus for emulating legacy instructions of a predetermined microprocessor defining a legacy environment, the apparatus comprising:

means for emulating said legacy instructions, said emulating means including a software routine for emulating various legacy instructions, the address of each software routine being identified by a vector:
means for translating said legacy instructions to a opcode/operand field and a vector/tag field, said vectors representing addresses of software routines for emulating said legacy instructions and said tags indexed to a table of thunk objects;
for said software routines for emulating said legacy instructions;
means for fetching said vector/tag field in response to request for said legacy instructions;
and
means for executing said software routines or said thunk objects in response to said fetching means.

3 more elements

Dependencies are inferred from the claim text.

Concurrent legacy and native code execution techniques

Life of this patent

Concurrent legacy and native code execution techniques

Life of this patent

Abstract

Claims10