Programmable delay path circuit and operating point frequency detection apparatus

A programmable frequency monitor circuit comprising:

• a programmable reference clock generator adapted to programmably generate a reference clock signal having a first frequency, said programmable reference clock generator comprising:
• a delay path circuit comprising delay cells coupled in series, each of said delay cells having a respective delay time associated therewith;
• and
• a delay cell controller coupled to each of said delay cells, said delay cell controller adapted to selectively activate a delay cell such that said programmable frequency monitor circuit can be programmably configured to have a selected delay associated therewith, wherein said selected delay is the sum of delay times associated with activated delay cells and wherein said selected delay is used for establishing said first frequency;
• a comparator coupled to said programmable reference clock generator and adapted to receive a system clock signal and said reference clock signal, wherein said svstem clock signal has a second frequency, said comparator further adapted to compare said system clock signal with said reference clock signal and generate an error signal when said second frequency of said system clock signal is different than said first frequency of said reference clock signal;
• and
• a frequency protection circuit coupled to said comparator and adapted to disable an integrated circuit when said error signal is generated;
• whereby said programmable frequency monitor circuit provides high and low frequency monitoring for integrated circuits having different system clock signal frequencies.