Memory controller, reproducing apparatus mounting the same and method for controlling the same
AssigneeSony Corporation
InventorYasuaki Maeda
Life of this patent
Estimating the term…
Abstract
A disc reproducing apparatus having a memory for temporary storage of data read from a disc. The memory is under the control of a memory controller which accesses data stored in the memory based on a generated address. The generated address is determined by a mode controller which can specify either the same address location, a previous location, or a later location depending upon the amount of data stored in the memory and errors which may occur in reading data from the disc.
Claims12
A disc reproducing apparatus in which after a sector consisting of sync data, header data, and digital data, and data stored in a recording medium is sequentially read for the sector and is written in a memory, the data stored in the memory is sequentially read and is reproduced, comprising:
- a memory controller which controls writing of data to the memory and reading of the data stored in the memory, wherein the memory controller comprises:
- a write address generator which generates a write address corresponding to a location in the memory in response to a mode signal;
- and
- a counter mode controller which generates the mode signal to control the write address generator and switches a data reading and writing mode according to a control signal, wherein the modes for which the counter mode controller generates mode signals include a round mode in which the internal address of the memory generated by the write address generator corresponds to a same memory area as a currently specified memory area, a straight mode in which the internal address of the memory generated by the write address generator corresponds to a memory area after the currently specified area, and a retry mode in which the internal address of the memory generated by the write address generator corresponds to a memory area previous to the currently specified area, the generated address including an address corresponding to a memory area not immediately previous to the currently specified area;
- and
- a controller which controls the operation of the memory controller by generating a control signal which controls the operation of the counter mode controller.
A memory control circuit for controlling a memory in which after stored data is sequentially read from a recording medium for a sector unit including sync data, header data, and digital data, and is written in a memory, the data stored in the memory is sequentially read for each sector, comprising:
- a) a signal processor which extracts the sync data of the sector and determines a status of the sector;
- b) a counter mode controller which controls a mode according to data from a controller and the status of the sector;
- c) a read out address generator which generates a read out address corresponding to a location in the memory according to the mode specified by the counter mode controller and the sync data from the signal processor;
- and
- d) a controller which controls writing of data to the memory and reading of data from the memory according to the memory address specified by the read out address generator;
- wherein the modes for which the counter mode controller generates mode signals include:
- 1) a round mode in which the internal address of the memory generated by the write address generator corresponds to a same memory area as a currently specified memory area;
- 2) a straight mode in which the internal address of the memory generated by the write address generator corresponds to a next memory area after the currently specified area;
- and
- 3) a re-try mode in which the internal address of the memory generated by the write address generator corresponds to a memory area previous to the currently specified area, the generated address including an address corresponding to a memory area not immediately previous to the currently specified area;
- and
- wherein the write address generator further includes:
- i) a sector counter for counting a sector number of data inputted with sector unit, wherein the data is divided into sectors having a sector number with each sector containing a predetermined amount of data;
- ii) a calculator for converting the value counted by the sector counter from a sector number to a byte number;
- iii) a byte counter for counting the added result for each byte according to a count up signal from the memory controller;
- and
- iv) an adder for adding the result of the calculator and the result of the byte counter.
A memory control method for controlling a memory, in which after data is sequentially read out from a recording medium for a sector unit including sync data, header-data, and digital data, and is stored in the memory, the data stored in the memory is sequentially read out for the sector unit and written, comprising the steps of:
- initializing an address of an address generating circuit;
- setting a memory controller to a round mode;
- determining that sync data has been generated;
- determining whether the generated sync data corresponds to a target sector;
- setting the memory controller to a straight mode when the sync data corresponds to the target sector;
- determining whether sector data previously written is correct;
- and
- setting the memory controller to a retry mode when the sector data previously written is not correct.
A disc reproducing apparatus in which after a sector consisting of sync data, header data, and digital data, and data stored in a recording medium is sequentially read for the sector and is written in a memory, the data stored in the memory is sequentially read and is reproduced, comprising:
- a memory controller which controls writing of data to the memory and reading of the data stored in the memory, wherein the memory controller comprises:
- a write address generator which generates a write address corresponding to a location in the memory in response to a mode signal;
- and
- a counter mode controller which generates the mode signal to control the write address generator and switches a data reading and writing mode according to a control signal, wherein the modes for which the counter mode controller generates mode signals include a round mode in which the internal address of the memory generated by the write address generator corresponds to a same memory area as a currently specified memory area, a straight mode in which the internal address of the memory generated by the write address generator corresponds to a memory area after the currently specified area, and a re-try mode in which the internal address of the memory generated by the write address generator corresponds to a memory area previous to the currently specified area, the generated address including an address corresponding to a memory area not contiguous to the currently specified area;
- and
- a controller which controls the operation of the memory controller by generating a control signal which controls the operation of the counter mode controller.
Dependencies are inferred from the claim text.