Method and apparatus for setting write latency
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson
Life of this patent
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Abstract
A method of setting write latency and a write/valid indicator circuit for use with the method. In a preferred embodiment, time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. The write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal, and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.
Claims27
A method of setting write latency in a memory device, the method comprising:
- detecting a first transition of a first signal;
- detecting a second transition of the first signal;
- detecting a transition of a second signal;
- establishing an end of a first time region at time T1 after the first transition of the first signal;
- establishing an end of a second time region before the second transition of the first signal:
- and
- indicating whether the transition of the second signal occurs between the end of the first time region and the end of the second time region.
A method of setting write latency in a memory device, the method comprising:
- detecting a preamble of a clock signal;
- establishing an acceptable time region to receive a write enable signal within the preamble;
- detecting the write enable signal;
- and
- indicating whether the write enable signal transitioned within the acceptable region.
A method of setting write latency in a memory device, the method comprising:
- delaying a first signal and indicating whether a transition of the delayed first signal occurs prior to a transition of a second signal;
- delaying the second signal and indicating whether a transition of the delayed second signal occurs prior to a transition of an undelayed first signal;
- and
- indicating an acceptable write latency setting if the transition of the delayed first signal occurs prior to the transition of the second signal and the transition of the delayed second signal occurs prior to the transition of the undelayed first signal.
Dependencies are inferred from the claim text.